Verilog-ALTERA/Datapath/Synchronous Controller Design

Hi, I need project to be do in Verilog, altera. The project is Datapath/Synchronous Controller Design which about design circuit that computes the numerical inverse of an 8-bit unsigned number will be designed and implemented. Let me know if you need more details.​ ​In this link [login to view URL]~mitch/class/5387/labs/project/[login to view URL] Do just part 1&2 ​ ​-----------------------------------------------------------------------------------------​ here is lab 3 link:​( two parts​ above ​ and I will provide you with little help such as experiment 3 files since I done it !!)​ [login to view URL]~mitch/class/5387/labs/lab3/[login to view URL] the file in the attachments File: lab 3 attached which I did it !! in this link : [login to view URL] Hi, I draw part 1 to u in the attachment who should be look like. Also, we need to use 2 mults and one sub to operate the formula. The project should be done in altera Quartus II 9.1sp1 and must be in written by Verilog. It should be match the golden waveform file. Don't forget the full credit part in part 2, please. See file :drawing 1 attached