Fpga project

$10-30 USD

Slutfört

Publicerad

nästan två år sedan

$10-30 USD

Betalning vid leverans

1. "idle" state: It is the state when the machine is doing nothing and is idle. In "idle" state, if power button is "on" then the state transition takes place from state "idle" to state "a" and the output is low. If power button is "off ", then the state remains in "idle". 2. "a" state: In state "a", if fill_water is 1(that is if the water gets filled) then the state moves to state "b" otherwise it remains in state "a". 3. "b" state: It is the wash state of the machine. In "b" state, if add_det = 1(that is if the detergent is added) then the state moves to state "c" otherwise remain at state "b". 4. "c" state: It is the rinse state of the machine. In "c" state, if the water is filled that is if fill_water = 1, then the process gets completed and the state returns back to its idle state and the output is 1. Otherwise it remains in state "c". and in state a it depends on weight for example : 0-2 kilo 3 seconds to fill water 3-5 kilos 5 seconds 6-7 kilos 8 seconds for the weight 3bit for the switches we want it in verilog code and the state diagram and FPGA DEMONSTRATION and testbench code

Verilog / VHDL

Electrical Engineering

Electronics

FPGA

Project ID: 33723602

Om projektet

9 anbud

Distansprojekt

Senaste aktivitet två år sedan

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Tilldelad till:

@ahmedmohamed85

$0 USD Om 1 dag

4,9

(500 omdömen)

8,1

9 frilansar lägger i genomsnitt anbud på $51 USD för detta uppdrag

@kingch91

Greetings This is Ahmed. I am a full time freelancer and Electronics Engineer. I can do this FPGA Task for you with high quality. However, some questions are still needed to be answered from your side if we interact. I will wait for your reply to complete your task within a given time. Thanks & Regards Ahmed.

$80 USD Om 7 dagar

4,9

(156 omdömen)

6,6

@Engrusman877

Hi There, I am a senior PhD Level Expert and Have more than 5 years of experience in electronics and verilog/VHDL coding. Just check my profile and share your details. Time and Budget will be discussed. Thanks

$100 USD Om 7 dagar

4,8

(70 omdömen)

5,9

@senthilps3

Hi I am a circuit designer using Verilog/VHDL, I have certain experience in finite state machine for some application interfaces with FPGA. You can check my profile for recent projects in Verilog and FSM. Kindly share your details on chat Thank you

$30 USD Om 3 dagar

5,0

(16 omdömen)

3,7

@TarekANasser

Greetings, I'm a digital IC designer. I'm experienced in Verilog and System verilog for verification. I'm also good at designing combinational and sequential logic. I've designed lots of RTLs before and I think I can do your job with the highest quality. Sincerely, Tarek

$30 USD Om 2 dagar

5,0

(5 omdömen)

3,4

@mhmdahmd789

i am more than capable to do this project also being Arab will help us communicate better , i have done several Embedded system projects but this will be my first FPGA Project thats why i will be cheaper

$10 USD Om 7 dagar