VLSI Design Engineer - Part Time

₹1500-12500 INR

Avslutat

Publicerad

över fem år sedan

₹1500-12500 INR

Betalning vid leverans

Front End VLSI Design engineer Part Time in Bangalore Looking for expert FPGA Design engineer with RTL Design [Verilog] Proven track record of designing, developing, prototyping, and testing high speed FPGA designs Experience in Verilog programming & experience with Xilinx devices and development tools Design Simulation experience [Modelsim] Candidate should be familiar with solving IEEE research papers, algorithms, architectures using VerilogHDL.

Electronics

FPGA

Verilog / VHDL

Project ID: 17806356

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9 anbud

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9 frilansar lägger i genomsnitt anbud på ₹9 527 INR för detta uppdrag

@ducdctoandh

Dear customer, I am really happy to help you out of this project. I would like to introduce that I am an freelancer with 100% JOB COMPLETED in VHDL/VERILOG. I am really suitable for job description: First: I am an Electronics engineer who is very expertise with VHDL/Verilog. In fact, I have done so many project of VHDL/Verilog(Karatsuba multiplier, Nintendo design, encryption algorithm like Sax Hash, Bernstein Hash, HummingBird...Also, I participated in a Walker Recognition project(data from Camera to Human Detection(image processing-HOG feature and Adaboost) and display in VGA). Besides,,I implemented the image conpression (wavelet transform). Aslo, I have experience in coding Booth multiplier and very familiar with Xilinx tools like ISE. and Vivado. Therefore, I can simulation the projecthe in behavior, post-syntheize... with free hesitation. I am also have experience of freelancer here: https://www.freelancer.com/u/ducdctoandh.html Also, I am very good in English (IELTS 6.0) and I have several year of researching so I can fully understand your requirement and understand fully about the papers and write the academic report. Please contact me and let me know if you want any special requirement and do with lower price. Thank you.

₹13 888 INR Om 3 dagar

4,9

(94 omdömen)

6,9

@raulbehl

Hello! Please check my profile and reviews to know a bit about me and my work. It would be great if I could help you out.

₹12 500 INR Om 7 dagar

4,9

(83 omdömen)

6,3

@hungfreelancer

Hello, I am working in the ASIC design flow for 10 years. I have experience in using VCS, modelsim, vivado FOR SIMULATION, DC for synthesis and ICC for layout. I have just completed the RTL and Testbench code for design multi core chip with 16 core of 16bit MIPS such that I think I can do your task very well. Best Regard.

₹1 500 INR Om 3 dagar

5,0

(8 omdömen)

4,2

@prsingla19

Hi, I have done my Mtech in VLSI design. I had also done my thesis on FPGA implementation of multiplier using verilog on Xillinx. please give me one chance.

₹13 888 INR Om 7 dagar

0,0

(0 omdömen)

0,0

@ibnuhasan

Currently working in Qualcomm. This maybe my first project in Freelancer, so im giving you very cheap quote.

₹7 777 INR Om 3 dagar

0,0

(0 omdömen)

0,0

@Aaryajaya

Has 3yr of experience in RTL design and Test bench writing in VHDL/ Verilog/ System verilog . Handled many FPGA related project from RTL design( in both Verilog/VHDL) to bring up . worked on : UART,I2C,SPI,Ethernet(RGMII,XGMII),DDR3,DAC,SERDES.. Thank you.

₹11 111 INR Om 3 dagar