Hung P.

10+ years experienced in ASIC Verification and Design. 4 years experienced in management of Verification team. Experienced in verifying IPs, MCU/uP Core, SoC subsystem and full SoC system. Experienced in verifying PCI 2.0, AMBA Buses (AHB, AXI, APB), SDRAM/SRAM/FLASH Memory CTRL, USB 2.0, I2S, GPIO, GPS Receiver, UART, TIMER, Watch-dog Timer, Interrupt Controller. Experience in verifying and designing the 8-bit chips and 32-bit chips Experience in designing Verification IPs (AHB master and slave VIPs), reference models (8-bit/32-bit C/C++ Instruction Set Simulator), Bus Functional Model (HF/UHF RFID Reader model). Experienced in (VMM) in building a verification environment for ASIC design. Experienced in using Verilog, SystemVerilog, C/C++, Assembly, Bash-Shell, Perl. Experienced in using EDA tools of: VCS, CustomSim-XA, MVSIM, QuestaSim, Vivado, Quartus II, can adapt with new tools. Good knowledge about Dynamic Power Simulation, Mixed-Signal Simulation, DFT.