Design the instruction set for the reduced instruction set (RISC) processor. 9-Bit ISA

In this project, you will design the instruction set for your own special-purpose reduced instruction set (RISC) processor. You will design the hardware for your processor core in subsequent projects. Your processor will have 9-bit instructions (machine code) and will be optimized for three simple programs, described below. For this project, you will design the instruction set and instruction formats and code three programs to run on your instruction set. Given the tight limit on instruction bits, you need to consider the target programs and their needs carefully. The best design will come from an iterative process of designing an ISA, then coding the programs, redesigning the ISA, etc. Your instruction set architecture shall feature fixed-length instructions 9 bits wide. Your instruction-set specification should describe: ● What operations it supports and what their respective opcodes are. For ideas, see the MIPS, ARM, and/or SPARC instruction lists ● How many instruction formats it supports and what they are (in detail -- how many bits for each field, and where they’re found in the instruction). Your instruction format description should be detailed enough that someone could write an assembler (a program that creates machine code from assembly code) for it. (Again, refer to ARM or MIPS.) ● The number of registers, and how many general-purpose or specialized. All internal data paths and storage will be 8 bits wide. ● Addressing modes supported (this applies to both memory instructions and branch instructions). That is, how are addresses constructed or calculated? Lookup tables? Sign extension? Direct addressing? Indirect? Immediate? For more info check out the attached file