I need solution some exercises from book "Parallel Computer Architecture - A Hardware/Software Approach" by Culler and Singh (ISBN 1-55860-343-3). It will be just 5.10 and 5.12 on page 370 and 371.
Below is sample from assignement:
5.10
Consider a four-processor bus-based multiprocessor using the Illinois MESI protocol. [..........]
a. What is the least number of transactions executed to get from the initial to the final state ?
b. What is the worst-case number of transactions ?
c. Repeat parts (a) and (b) assuming the Dragon protocol.
5.12
Suppose all 16 processors in a bus-based machine try to acquire a test-and-test&set lock simultaneously (and only once each). [..........]
a. How many bus transactions will it take until all processors have acquired the lock if all the critical sections are empty (i.e. each processor simply does a LOCK and UNLOCK with nothing in between) ?
b. ... c. ... d. ... e. ...
If you know you can do or already have solution with good explanation thanks for bidding.
Thanks for helps.
## Deliverables
1) Complete and fully-functional working program(s) in executable form as well as complete source code of all work done.
2) Deliverables must be in ready-to-run condition, as follows (depending on the nature of the deliverables):
a) For web sites or other server-side deliverables intended to only ever exist in one place in the Buyer's environment--Deliverables must be installed by the Seller in ready-to-run condition in the Buyer's environment.
b) For all others including desktop software or software the buyer intends to distribute: A software installation package that will install the software in ready-to-run condition on the platform(s) specified in this bid request.
3) All deliverables will be considered "work made for hire" under U.S. Copyright law. Buyer will receive exclusive and complete copyrights to all work purchased. (No GPL, GNU, 3rd party components, etc. unless all copyright ramifications are explained AND AGREED TO by the buyer on the site per the coder's Seller Legal Agreement).
## Platform
Parrallel Computer Architecturre