Quick help needed on coming up with a dynamic Allocation of 2-Dimension System Verilog port

$10-30 USD

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över ett år sedan

$10-30 USD

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I have a localparamter declared in my SystemVerilog like this (y is another Parameter) : localparam x = y ? 4 : 1 , Then I have a RTL port which is something like this (where z is another parameter): input logic [x-1:0][((z+1)*8-1):0] port1, But I want to use 'y' directly in this port1 instead of x. Can I somehow use 'y' instead of x to dynamically allocate the value of it. It should be able to compile/elaborate. Should be quick

Project ID: 35172450

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@nhannguyen711

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$30 USD Om 2 dagar

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@aaliyahnza

Valuable client I'm expert electrical engineer with more than 4 years of experience in Arduino, Verilog, VHDL coding. I can assist you in your question. Looking forward to hearing from you. Thanks

$30 USD Om 1 dag