Fix Cadence XOR gate schematic

A highly-skilled FPGA engineer with 7+ years experience and hundreds of FPGA/Verilog/VHDL projects using Xilinx/Altera FPGA Design Tools and Digital Logic Design using LogiSim/CEDAR. Founder of FPGA4student. Expertise: FPGA, Verilog, VHDL, Xilinx ISE, Vivado, Altera Quartus, Modelsim, Logisim, CEDAR, MIPS Assembly, PLP Tools, Qtspim, MARS, PCB Design, Altium Designer, OrCAD, PSpice, Proteus, Arduino, CMOS VLSI Design, Cadence Virtuoso, Layout XL, Digital IC Design from RTL to GDSII, Analog IC Design. - Featured FPGA projects: + Video/Image Processing on FPGA: FPGA/Verilog/VHDL Implementation of Gesture Recognition, Fingerprint Identification, Image Compression in Wavelet Domain using DWT and SPIHT, Image Enhancements including Noise Filtering. + Fixed-point and Floating Point FPGA projects in Verilog/VHDL + AES, SHA 128, 192, 256 Implementations on FPGA + Single/Multicycle/Pipelined RISC/MIPS Processors in Verilog/VHDL/Logisim + Games on FPGA and many other FPGA projects

Am full-time freelancer expert in Electrical & Electronic Circuit Designing & Simulation, PCB Designing, Consultancy of different types of Electrical & Electronic Problem. I can write Fix Cadence XOR gate schematic, I am ready to give hardworking, reliability, flexibility & honesty. I can work with minimal supervision, communicate & give updates on the status of my work output. I am always determined to deliver projects to freelancer clients before meeting the deadline with 100% satisfaction & loyalty.

Hi, I am an IC Mask Layout Design Engineer. I can fix your problem in less than 1 hour. I have experience to design layout in TSMC/GF/XFAB/NCSU PDK @7/16/22/130/180nm node. I have Cadence Virtuoso also. I think you are working with NCSU PDK. So I can work in my PC too, you just need to send the layout and schematic to fix Waiting for your response...

Hello, I've read your job description and I can help you with this task because I've 5+ years of experience using Cadence Virtuoso for all layers of VLSI design. I've faced this exact issue myself for there is a reason why this happens and can correct it for you. I can either use TeamViewer to correct your schematic on your Cadence tool or draw stick diagram on paint and send you, whatever you prefer. Please let me know. I'll be looking forward to work with you. Thanks.

Hello, I am an electronics engineer having experience in design using cadence virtuoso for more than 5 years.

I can design this Relevant Skills and Experience I am electronic engineer , I can design xor gate for ypu